With increasing popularity of electronic devices, such as laptop computers, portable digital assistants, digital cameras, mobile phones, digital audio players, video game consoles and the like, demand for non-volatile memories are on the rise. Non-volatile memories come in various types, including flash memories. Flash memories are widely used for rapid information storage and retrieval in electronic devices such as those mentioned above.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration or each is arranged. FIG. 1 illustrates a typical NAND flash memory array 10 of conventional design. The array 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, one of which is shown in FIG. 1. Each block includes a number of rows, which, in the example shown in FIG. 1, includes 32 rows. The cells 14 in the same row have their control gates coupled to a common word line 30, each of which receives a respective word line signal WL0-WL31.
As also shown in FIG. 1, the cells 14 in the same column have their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 20 through a first select gate transistor 24. The conductive state of the transistors 24 in each block are controlled by a select gate SG(D) signal. Each of the bit lines 20 output a respective bit line signal BL1-BLN indicative of the data bit programmed in the respective column of the array 10. The bit lines 20 extend through multiple blocks to respective sense amplifiers (not shown). The source of the lower flash memory cell 14 in the block is coupled to a source line 26 through a second select gate transistor 28. The conductive state of the transistors 28 in each block are controlled by a select gate SG(S) signal.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell 14. This can be accomplished by storing multiple levels of charge on the floating gate of each cell 14. These memory devices are commonly referred to as multi-bit or multi-level flash memory cells, known as “MLC memory cells.” In MLC cells, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are programmed into a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. For example, for a flash memory cell to be programmed with 2 bits of data, 4 distinct threshold voltage levels corresponding to bit states 00, 01, 10, and 11 are needed. When reading the state of the memory cell, the threshold voltage level for which the memory cell 14 conducts current corresponds to a combination of bits representing data programmed into the cell.
During the life of a non-volatile memory cell, the cell will typically be cycled through many program and erase operations as different data is programmed in, erased from, and read from the cell. Repeated use of the memory cell over time, including hundreds or thousands of such cycles, causes its operation to drift and its response to voltage applied to place the cell in a given threshold voltage state to change the threshold voltage necessary to erase or program the cell changes. FIG. 2A generally depicts the threshold voltage necessary for programming and erasing a cell drifting over many cycles for a given program pulse with a constant magnitude and time. Therefore to maintain the required erase and program threshold voltage level a change in voltage and/or duration is needed. FIG. 2A shows the case where the cell becomes harder to erase but easier to program. In FIG. 2A, the voltage necessary to perform these operations drifts in the same direction. For example, if the threshold voltage necessary to erase or program the cell moves up, the cell becomes harder to erase in that a larger voltage will be necessary to erase the cell, while the cell is easier to program in that a smaller voltage will be sufficient to program the cell. The threshold voltages can also drift in the opposite directions such that the cell becomes harder to program and easier to erase. Further, the threshold voltages necessary to program and erase themselves may, under some conditions drift in opposite directions, as shown in FIG. 2B, such that the difference between the voltage necessary to erase and the voltage necessary to program (the “window”) becomes smaller.
Accordingly, there is a need for, among other things, a system including a non-volatile memory array that accommodates drifting threshold voltages of cells in the array.